Logic Gates Circuit Trainer

Output d.c. Voltage : fixed 5v ±1%
output current : 1 amp
load regulation : ±1% of the highest specified output voltage
(no load to full load)
line regulation (for ±10% change : less than 50 mv. In mains voltage i.e. 230v)
ripple and noise : less than 5 mv
clock input device : clock pulse of 1 second
debounced logic switch (hilo) : four nos. Input voltage of hi level ³ 2.25v. Input voltage of lo leve £ l 0.8v
4 bits led output indicator : maximum input voltage less than or equal to 5v d.c.
Solder less bread board : bread board having one main strip, total interconnected 640 tie points for ics and half main strip, total interconnected 320 tie points for power supply, clock, input and output state. Each strip having length 173mm and accepting dia 0.56mm24swg recommended, use only 22-26 swg wire for interconnections
basic logic gates & : four and gates, four or gates, four nand gates, four nor gates, six not
flip flop units gates, dual j-k flip-flop, j.k. Masterslave flip-flop & dual d-type flip flop
applications: verification of and, or, not, nand, nor gates & their truth table. Verification of boolean algebra. The half-adder and full-adder design. Verification of d-type flip-flop and truth table. Verification of jk flip-flop and truth table. Verify cation of dual jk masterslave flip-flop and truth table
features:
the unit is operative on 230v ±10% at 50hz a.c. Mains
strongly supported by detailed operating instructions, giving details of object, theory, design procedures, report suggestions and book references
optional accessories:
jumper wire bag (4 reels, 5mreel),cutter stripper tool
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